1. Technical Field
The embodiments described herein relate to semiconductor circuit technology and, more particularly, to a semiconductor memory apparatus capable of improving precharge performance.
2. Related Art
As shown in FIG. 1, a conventional semiconductor memory apparatus includes a plurality of memory banks BANK 0 to BANK 15, a plurality of column decoders 10, a plurality of write drivers (WDRV) 20, and a plurality of IO sense amplifiers (IOSA) 30. The decoders 10 are respectively disposed in one-to-one correspondence with the memory banks BANK 0 to BANK 15. Each memory bank group includes one write driver 20 and one IO sense amplifier 30.
Still referring to FIG. 1, the semiconductor memory apparatus can further comprise a plurality of memory bank groups of which memory bank group 101 is shown as a representative example. A memory bank group has a plurality of memory banks (for instance, BANK 0, BANK 1, BANK 8 and BANK 9), which are aligned in the same vertical line. The write driver 20 records data, received from outside the circuit, in the presently activated memory bank of a corresponding memory bank group through a data input/output line, or local IO line, (nor shown). When data is to be read out, the IO sense amplifier 30 detects data read out of a memory bank in an associated memory bank group, via the local IO line, amplifies and outputs the data.
As can be seen, the write driver 20 has a precharge circuit unit 40. FIG. 2 is a diagram illustrating the write drive 20 for memory bank group 101 in more detail. Specifically, the connection structure between the precharge circuit unit 40 and the local IO line will be described with reference to FIG. 2. Elements, which have no direct connection to the precharge circuit unit 40, are omitted from FIG. 2.
As shown in FIG. 2, the precharge circuit unit 40 is commonly connected to the memory banks BANK 0, BANK 1, BANK 8 and BANK 9 through the local IO lines LIO and LIOB. The precharge circuit unit 40 can precharge the local IO lines LIO and LIOB to a predetermined voltage level whenever data input/output operations are not being performed through the local IO lines LIO and LIOB.
FIG. 3 is a timing diagram illustrating the precharge operation of the conventional semiconductor memory apparatus having the above structure. Generally, The precharge operation must be performed after a current write or read operation is completed and before the next write or read operation is to occur.
The data input/output operation is performed through the local IO lines LIO and LIOB while a column selection signal Yi is being activated according to a write or read command. If the column selection signal Yi is activated, the precharge signal LIOPCG is not activated. In contrast, if the column selection signal Yi is not activated, the precharge signal LIOPCG is activated. As the precharge signal LIOPCG is activated, the precharge circuit unit 40 shown in FIG. 2 precharges the local IO lines LIO and LIOB.
Referring again to FIG. 2, in a conventional semiconductor memory apparatus, a plurality of memory banks are vertically aligned and the local IO lines LIO and LIOB are connected to the memory banks. As the length of the local IO lines LIO and LIOB increases, a line load also increases due to the inherent resistance and capacitance of the lines. If the line load is increased, the precharge time is also increased as represented by A, A′, B and B′ in FIG. 3.
If the precharge time increases, then certain operational characteristics of the conventional semiconductor memory apparatus, such as tCCD (CAS to CAS command delay) and tWRT (Internal WRITE to READ command delay) shown in FIG. 3, can deteriorate, lowering the operational speed of the semiconductor memory apparatus. If the operational speed of the semiconductor memory apparatus is excessively lowered, the operational characteristics of the semiconductor memory apparatus may deviate from the standard thereof.